Mosfet PowerPoint Presentation

7/29/2019 Mosfet PowerPoint Presentation

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MOSFET(Metal Oxide SemiconductorField Effect

Transistor)

Presented By- Moh


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Transistors

These are three terminaldevices, where the current orvoltage at one terminal, theinput terminal, controls theflow of current between thetwo remaining terminals.


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Current Controlled vs Voltage Controlled Device


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Current Controlled vs Voltage Controlled Devices


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Transistors

Can be classified as: FET Field Effect Transistor;

Majority carrier device;

Unipolar device;

BJT Bipolar Junction Transistor; Minority carrier device;

Bipolar device.


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FETs

Two primary types: MOSFET, Metal-Oxide-Semiconductor FET. Also

known as IGFET Insulated Gate FET; JFET, Junction FET.

MOS transistors can be: n-Channel;

Enhancement mode; Depletion mode;

p-Channel; Enhancement mode; Depletion mode;


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Overview

Types of FET

p-channelJFET n-channel

MOSFET

p-channel

n-channel

enhance

depletion

enhancedepletio


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The MOS Transistor

PolysiliconAluminum


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Metal Oxide Semiconductor FET: MOSFET

MOSFET also known as insulated-gate field-etransistors (IGFET) is preferred in power electronics duits ability offastswitchingespecially in timing circuits.

MOSFET has a "Metal Oxide" gate (silicon dioxide- usa glass, with insulating properties), which is electrinsulated from the semiconductors N-channel or P-cha

This isolation of the controlling gate makes the resistance of the MOSFET extremely high in the Mohms region (infinite), thus switching lossat input sidecontrolled and stabilized.

As the gate terminal is isolated from the main cucarrying channel "NO current flows into the gateMOSFET acts as a voltage controlled resistor (like JFET

MOSFET is specially used in digital complementary m

oxide semiconductor (CMOS) logics.


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Metal Oxide Semiconductor FET: MOS


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MOS gate Structure

First electrode - Gate :Consists of low-resistivitymaterial such as highly-dopedpolycrystalline silicon,aluminum or tungsten

Second electrode - Substrateor Body: n- orp-typesemiconductor

Dielectric - Silicon dioxide:stable high-quality electricalinsulator between gate andsubstrate.


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MOS Capacitor Picture


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MOS Electrostatics

Condition is called flatband --- the voltage when this occursis called flatband

This state is the baseline operating case --- a capacitivedivider has one free parameter

Vfb


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MOS Electrostatics

Depletion Condition --- gate charge is terminated by chargedions in the depletion region

Part of this region is often referred to as weak-inversion


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MOS Electrostatics

Inversion --- further gate charge is terminated by carriersat the silicon--silicon-dioxide interface


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MOSFET FAMILY-TREE


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MOSFET Circuit Symbols

(g) and (i) are the most

commonly usedsymbols in VLSI logicdesign.

MOS devices aresymmetric.

In NMOS, n+region athigher voltage is thedrain.

In PMOS p+region atlower voltage is thedrain

i


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Output current (Drain current-ID) in a MOSFET is controlled by the gsource voltage VGS.

VGS controls the thickness of the channel

MOSFET Operation


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Ch l MOSFET With VGS VT


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n-Channel MOSFET With VGS > VT , sm


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n-Channel MOSFET With VGS > VT , large V


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MOSFET Regions of Operation

MOSFET R i f O ti


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MOSFET Regions of Operation


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I-V Characteristics of MOSFET


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The drain current versus the drain-to-source voltagfor an enhancement-type NMOS transistoroperated.


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MOSFET ID-VG, ID-VDS

OFF

ON

ID

VGS =VDD

VGS1

VGS2

VGS3

ID

VGS

VDS = Kostant

ID

D

S

GVDS

VGS

AnalogDigital Logic

D or S

Gat

VTN

VDD= 1

MOSFET M d f O ti


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MOSFET Modes of OperationsTwo basic types of MOSFETs:

1. Depletion MOSFETs (D-MOSFETs): can be operated in eitthe depletion mode or the enhancement mode (Negative VG

2. Enhancement MOSFETs (E-MOSFETs) : can be operated oin the enhancement mode (Positive VGS).

E-MOSFET: ZD-MOSFET: Zero bias


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DEPLETION TYPE MOSFET

A CONDUCTING CHAN

ALREADY EXISTS DEVICE IS NORMALLY

NO BIAS APPLIED TO G

THE DEVICE CAN OPEEITHER IN THE ENHANMODE BY APPLYING A

GATE VOLTAGE OR IN ADEPLETIONMODE WITNEGATIVE BIAS ON TH

Depletion Mode MOSFET Construction


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Depletion Mode MOSFET Construction

The Drain (D) and Source (S) leads connect to the to n-doped regionsThese N-doped regions are connected via an n-channelThis n-channel is connected to the Gate (G) via a thin insulating layer ofSiO2The n-doped material lies on a p-doped substrate that may have an additerminal connection called SS

Basic Operation


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Basic Operation

A D-MOSFET may be biased to operate in two modes:the Depletion mode or the Enhancement mode

D-MOSFET Depletion Mode Operation


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D MOSFET Depletion Mode Operation

The transfer characteristics are similar to the JFETIn Depletion Mode operation:When VGS = 0V, ID = IDSSWhen VGS< 0V, ID < IDSSWhen VGS > 0V, ID > IDSSThe formula used to plot the Transfer Curve, is:

2GS

D DSS

P

VI = I 1 -

V

D-MOSFET Enhancement Mode Operation


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D-MOSFET Enhancement Mode Operation

Enhancement Mode operation

In this mode, the transistor operates with VGS > 0V, and ID increases above IDSShockleys equation, the formula used to plot the Transfer Curve, still applies VGS is positive:

2GS

D DSS

P

VI = I 1 -

V

p-Channel Depletion Mode MOSFET


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p p

The p-channel Depletion mode MOSFET is similar to the n-channel except tthe voltage polarities and current directions are reversed


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ENHANCEMENT TYPE MOSFET

THE ENHANCEMEN

MOSFET IS NORMALLY NO CURRENT

BETWEEN THE SOUTHE DRAIN FOR VG=0

THE CHANNEL IS INDAPPLYING A VOLTAPPROPRIATE POLATHE GATE.

Enhancement Mode MOSFET Construction


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The Drain (D) and Source (S) connect to the to n-doped regionsThese n-doped regions are not connected via an n-channel without an externavoltageThe Gate (G) connects to the p-doped substrate via a thin insulating layer ofSThe n-doped material lies on a p-doped substrate that may have an additionaterminal connection called SS

E-MOSFET Symbols


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Basic Operation


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The Enhancement mode MOSFET only operates in the enhancement mode.

VGS is always positiveIDSS = 0 when VGS < VT

As VGS increases above VT, ID increasesIf VGS is kept constant and VDS is increased, then ID saturates (IDSS)The saturation level, VDSsat is reached.

Transfer Curve


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To determine ID given VGS:where VT = threshold voltage or voltage at which the MOSFET turns on.k = constant found in the specification sheetThe PSpice determination of k is based on the geometry of the device:

2D GS T

I = k (V - V )

D(on)

2GS(ON) T

Ik =

(V - V )

N OX

W KPk = where KP = C

L 2

p-Channel Enhancement Mode MOSFETs


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The p-channel Enhancement mode MOSFET is similar to the n-channel excethat the voltage polarities and current directions are reversed.

TYPES OF MOSFET


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Summary Table


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JFET D-MOSFET E-MOSFET

Non-ideal MOS


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So far, we have discussed MOS characteristicsmaking some assumptions - calling it ideal.

Assumed that the M = S , i.e. the bands are flat whenno voltage is applied.

Assumed that the oxide and oxide-semiconductorinterface are free of charges.

These assumptions do not hold good in an actual

MOS device, and we have to consider thedeviations from the ideal case. For the purpose ofdiscussions, we call these as real.

Metal-semiconductor work function differen


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Metal semiconductor work function differenWhen M = S , the Fermi level is aligned before we make the device. So, when the

MOS structure is made, the band remains flat when the applied gate voltage is zero.

AssumptionMS =MS = 0

EFM

OM S

M

S

Flat band condition

Metal-semiconductor work function differe


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Metal semiconductor work function differe

M depends on the metal.

Example:M (Al) 4 eV, M (Au) 5.1 eV

S depends on the semiconductor doping.S = + (ECEF)FB

So,MS = MS 0

in a real device.

So, actual band alignment before

making the MOS-C structure looks as

shown for Al-Si (p)

EFM

OM S

M S

M = Al

Interface and oxide charges


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gFor the ideal device, we have assumed that the oxide and the

interface is devoid of any excess charges. This is not true in practice.

Si

+ + + + + + + + + + + + + + + + ++

+ + --

-- + -

Na+

Na+

Qit

Qof

Qof

Qmetal Assume that all these chargesare situated close to the interfaceon the oxide side (even thoughthey arent) and their concentrationis Qi Coulombs/cm

2.

Qi = net interface charges in C/cm2

Effect of interface charges, Qi(C/ 2)


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g(C/cm2)

The interface charge Qi in the oxide (assumed positive) will inducesome negative charges (-Qi /cm2) in the semiconductor. The effect

is as though we have applied a positive gate voltage to the gate, andthe negative charges in the semiconductor causes band bending. Toget flat-band condition, we have to apply a negative voltage to the gate.

Voltage to be applied to the

gate to get flat-band condition

oxox

i where CC

Q-

Qi is usually positive (but can be both positive or negative in general).

Effects of work function difference and interfac


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Effects of work function difference and interfacIf we consider the effects of work function difference and theinterface charges, the silicon band diagram may not be flat

even when no voltage is applied to the gate. Hence, a correctionhas to be applied to the threshold voltage calculations carried out

earlier assuming ideal MOS conditions.

-

ox

i

msFB

1

C

Q

qV

voltage to be applied to the gate toget flat band condition.=

'TFBT VVV

where VT is the threshold voltage assuming

ideal conditions


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Channel length modulation

The reverse biased p-n junctionbetween the drain and the body

forms a depletion region withlength L that increases with Vdb.The depletion region effectivelyshorten the channel length to:Leff= LL

Assuming the source voltage isclose to the body votage Vdb ~Vsb. Hence, increasing Vdsdecrease the effective channellength.

Shorter channel length results inhigher current


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Nonideal Effects..channel length modulation

DI

DD ILL

LI

-'

'

DI

Where is the actual drain current and is

the ideal drain current. Since is a function of

, is now also a function of even though

the transistor is biased in the saturation region.

DD ILL

LI

-'

L

'

DI

DSVDSV

ff


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Body Effect

The potential difference between source and body Vsb affects (incre

threshold voltage Threshold voltage depends on:

Vsb

Process

Doping

Temperature


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Sub-Threshold Conduction

Ideally at VGS < VT, ID = 0.

The MOS device is partially conducting forgate voltages below the threshold voltage.

This is termed sub-threshold or weak inversionconduction.

In most digital applications the presence ofsub-threshold current is undesirable.

A Sub-threshold digital circuit manages tosatisfy the ultra-low power requirement.

S bth h ld C d ti


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Subthreshold Conduction

Below cut off current does not abruptly become zero

Falls off exponentially

Useful in low power CMOS VLSI design

)1(0T

ds

T

tgs

v

V

nv

VV

dsds eeII-

-

-

8.12

0 evI Tds


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Nonideal Effects..subthreshold

--

kT

eV

kT

eVsubI DSGSD exp1exp

J ti L k


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Junction Leakage Conduction even when

transistor is in cut-off

Substrate to diffusionjunctions are reversebiased

However reverse

biased diodes doconduct leakagecurrent

)1( -T

D

v

V

SD eII

Junction Leakage


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Junction Leakage The p-n junctions between diffusion and the substrate or

well for diodes.

The well-to-substrate is another diode

Substrate and well are tied to GND and VDD to ensurethese diodes remain reverse biased

But, reverse biased diodes still conduct a small amount ocurrent that depends on:

Doping levels

Area and perimeter of the diffusion region The diode voltage

L k C t


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Leakge Current

When the junction bias voltage is significantly more tha

thermal voltage (~26mV @room temperature) the leakcurrent isIs

Junction leakage limits storage time in on-chip memoryelements

Requires refreshing dynamic nodes

Tunneling current


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Tunneling current

Current technology nodes

Tunneling current as significant as junction leakage and sub-conduction

Technique to reduce tunneling current Use high-K materials in the gate oxide layer

High dielectric constant makes high gate capacitance Reduces the need to reduce the oxide thickness

Silicon Nitride is a good candidate for such materials

Tunneling effects


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Tunneling effects

Ideal MOS model

High input impedence No static current flow through the gate terminal

Quantum mechanical effect Carriers tunnel through insulating barriers with finite probab

Insulating barrier has to be very thin for appreciable current

Current gate oxide thickness ~10-15 Single atomic layer of silicon ~3

Temperature Effects


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Temperature Effects

Effect on Mobility

Carrier mobilitydecreases withtemperature

k is a parameter usuallyin the range 1.2-2.0

k

r

rT

TTT

-

)()(

Temperature effects


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Temperature effects

Threshold voltage

Vt decreases linearly with increase in temperature

Junction leakage also increases with increase in tempe

All combined results in decrease of On current and incOff current

The Threshold Voltage


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The Threshold Voltage

Any gate-to-source voltage less than VT0 is notsufficient to establish an inversion layer.

The MOSFET conducts no current between itssource and drain terminals unless VGS isgreater than VT0.

Increasing the gate-to-source voand beyond VT0 will not affect th

potential and the depletion regio There are 4 physical properties t

threshold voltage namely (i) the difference between the gate and(ii) the gate voltage component tsurface potential, (iii) the gate vocomponent to offset the depletiocharge and (iv) the voltage comp

offset the fixed charges in the gain the silicon oxide interface.

qVT0

Ec

EiEFp

Ev

2FF-F

Metal (Al)

Oxide (SiO2)P-type Semiconductor (Si)

Velocity saturation and mobility degrad


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Velocity saturation and mobility degrad

At strong lateral fields

resulting from high Vds,drift velocity rolls off dueto carrier scattering andeventually saturates

Strong vertical fieldsresulting from large V

gs

cause the carriers toscatter against thesurface and also reducethe carrier mobility. Thiseffect is called mobilitydegradation

Nonideal Effects velocity saturation


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Nonideal Effects..velocity saturation

2/1

2

1

sat

eff

eff

v

E

N id l Eff bili i i


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Nonideal Effects..mobility variation3/1

0

0

-

E

Eeff

eff

0Where and are constants determined from

experimental results.0

E

Short Channel Effect


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Short Channel Effect

In small transistors, source/drain depletion regions extend into the cha Impacts the amount of charge required to invert the channel

And thus makes Vt a function of channel length

Short channel effect: Vt increases with L Some processes exhibit a reverse short channel effect in which Vt decrea

Hot-Carrier Effects


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Hot-Carrier Effects Channel electron

traveling throughhigh electric field

near the drain endcan:

become highly energetic, i.e. hot

cause impact ionization and generate e- and holes

holes go into the substrate creating substrate current, Isub.

Some channel e- have enough energy to overcome theSiO2-Si energy barrier generating gate current, Ig.

The maximum e-field, Em near the drain has the greatescontrol ofhot carrier effects.

Gate Ig

n+ Drainn+ Source

Isub

mholehot e-l

ll l l l l

Hot electrons

The channel Hot Electrons effect is caused by electrons


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The channel Hot Electronseffect is caused by electronsflowing in the channel for large VDS

e- arriving at the Si-SiO2 interface with enough kinetic

energy to surmount the surface potential barrier areinjected into the oxide

This may degrade permanently the C-V characteristics of MOSFETs

Hot Electron Effects


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Hot Electron Effects

Effect:

hot electron injection.

Outcome: substrate current.

Trends:

power supplies are decreasing electric fields are increasing.

Non-Ideal I-V Effects (Summary)


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Non Ideal I V Effects (Summary)

Miniaturization has led to modern deviceshaving nonideal characteristics

The saturation current increases less thanquadratically with increasing VGS.

Velocity saturation and mobilitydegradation are two of the effects thatcause the non quadratic current increasewith VGS.

When carrier velocity ceases to increaselinearly with field strength we havevelocity saturation.

The current IDS is lower than high VDS.

There are several sources ofresult in current flow when thexpected to be OFF.

The source and drain diffusioform reverse biased diodes wexperience junction leakagesubstrate or well.

The current into the gate IG ishowever as gate oxide thicknreduced electrons tunnel throcausing some current.

APPLICATIONS OF MOSFET


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C O S O OS

CAN BE USED AS A SWITCH

AS AN AMPILFIER DeepGATE power MOSFETs with increased voltage ratings, de

enhanced on-state and switching performance for DC-DC applic

For automotive applications

For space applications


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Thank You!

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