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A term paper submitted for the partial fulfillment of the course ECE 202

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Table of contents :

S. No. Contents Page No.

(From- To)

1. Introduction of PLDs 4

2. Advantages of PLDs 5

3. Types of PLDs 6

4. Programmable Logic Array 7-10

5. Programmable Array Logic 10-12

6. References

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1. INTRODUCTION [1][4]

A programmable logic device or PLD is an electronic component used to build reconfigurable

digital circuits. Unlike a logic gate, which has a fixed function, a PLD has an undefined function at

the time of manufacture. Before the PLD can be used in a circuit it must be programmed, that is,

reconfigured. PLDs were first introduced in the 1970s.

In fixed-function logic circuits (e.g. SSI, MSI, LSI, VLSI & ULSI), a specific logic function is

contained in the IC package when it is purchased and it can never be changed. PLDs are another

category of logic devices in which the logic function is programmed by the user and in some casescan be reprogrammed many times. The function provided by each of the 7400-series parts is fixed

and cannot be tailored to suit a particular design situation. This fact, coupled with the limitation

that each chip contains only a few logic gates, makes these chips inefficient for building large logic

circuits. It is possible to manufacture chips that contain relatively large amounts of logic circuitry

with structure that is not fixed.

It is a general purpose chip for implementing logic circuitry & contains a collection of logic circuit

elements that can be customized in different ways. A PLD can be viewed as a black box thatcontains logic gates and programmable switches. The programmable switches allow the logic gates

inside the PLD to be connected together to implement whatever logic circuit is needed.

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Fig 1.1(CPLD)

2. ADVANTAGES OF PLDS [1][4]

In many applications the PLD has replaced the hard-wired fixed-function logic devices. However,

fixed-function logic is still important and will be around for a long time but in more limitedapplications. The advantages of PLDs are:

I. Increased Integration : the package count of the design can be reduced whilesimultaneously increasing the features offered by the product.

II. Lower Power : CMOS and fewer packages combine to reduce power consumption.

III. Improved Reliability : Lower power plus fewer interconnections and packagetranslate into greatly improved system reliability .

IV. Lower Cost: PLDs reduce the inventory cost too.

V. Easier to Change: With certain PLDs, logic designs can be readily changedwithout rewiring of replacing components

VI. Easier To Use : Generally, a PLD can be implemented faster than one using fixed-function ICs once the required programming language is mastered.

VII. Another advantage of PLDs over fixed-function logic devices is that many morelogic circuits can be stuffed into a much smaller area with PLDs.

TYPES OF PLDs [1][b]

The three major types of programmable logic are SPLD, CPLD & FPGA. Each major typegenerally has several manufacturer- specific subcategories.

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PLA comprises a collection of AND gates that feeds a set of OR gates. A programmable logicarray (PLA) is a programmable device used to implement combinational logic

In digital circuit theory, combinational logic is a type of digital logic which is implemented byBoolean circuits, where the output is a pure function of the present input only. This is in contrast to

sequential logic, in which the output depends not only on the present input but also on the circuits.

Fig 4.1

The general structure of a PLA is depicted in the figure given below:

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Fig 4.2

As shown in the figure, the PLAs inputs x 1..x n pass through a set of buffers(which provide boththe true value and complement of each input) into a circuit block called an AND plane, or ANDarray. The AND plane produces a set of product terms P 1..P k . Each of these terms can beconfigured to implement any AND function of x 1..x n. The product terms serve as the inputs to anOR plane, which produces the outputs f 1.f m.

A more detailed diagram of PLA is given below

Fig 4.3 Fig 4.4

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The diagram shows a PLA with three inputs, four product terms, and two outputs. Each AND gatein the AND plane has six inputs, corresponding to the true and complemented versions of the threeinput signals. Each connection to an AND gate is programmable; a signal that is connected to anAND gate is indicated with a wavy line, and a signal that is not connected to the gate is shownwith a broken line. The circuit is designed in such a way that any unconnected AND-gate input donot affect the output of the AND gate. The AND gate that produces P 1 is shown connected to theinputs x 1 & x 2. Hence P 1=x1. x2. Similarly, P 2=x1 .x3, P3= x 1.x2.x3 &

P4= x 1.x3. Programmable connections also exist for the OR plane. Output f 1 is connected to the product terms P 1, P2, and P 3. It therefore realizes the function f 1= x1. x2 + x 1 .x3 + = x 1.x2.x3 .Similarly there is the output for f 2.

Commercially available PLAs come in much larger sizes. Typical parameters are 16 inputs, 32 product terms, and 8 outputs.

The PLA is efficient in terms of the area needed for its implementation on an integrated circuitchip. For this reason, PLAs are often included as part of larger chips, such as microprocessor.

EXAMPLE:

Given a group of functions.

F0 = A + B' C'

F1 = A C' + A B

F2 = B' C' + A B

F3 = B' C + A

Step 1: Minimize functionsFunctions already in minimized form.

Step 2: Look for common product terms:

A B, B C, A C, B C, A

Step 3: PLA table with Shared Product Terms.

Product term Inputs Outputs A B C F 0 F 1 F 2 F 3

A B 1 1 - 0 1 1 0B C - 0 1 0 0 0 1A C 1 - 0 0 1 0 0B C - 0 0 1 0 1 0A 1 - - 1 0 0 1

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Step 4: Draw PLA diagram.

Fig 4.4

4. PROGRAMMABLE ARRAY LOGIC [3][5][a]

In a PLA both the AND & OR planes are programmable. Historically, the programmable switches presented two difficulties for manufactures of these devices: they were hard to fabricate correctly,and they reduced the speed-performance of circuits implemented in the PLAs. These drawbacksled to the development of a similar device in which the AND plane is programmable, but the OR

plane is fixed. Such a chip is known as Programmable Array Logic (PAL) device. Because they aresimpler to manufacture, and thus less expensive than PLAs, and offer better performance, PALshave become popular in practical applications. Another disadvantage of the PLA was longer delays due to the additional fusible links that result from using two programmable arrays and morecircuit complexity. The PAL is the most common one-time programmable (OTP) logic devicesand is implemented with bipolar technology (TTL or ECL).

The PAL consists of a programmable array of AND gates that connects to a fixed array of OR gates. This structure allows any sum-of-products (SOP) logic expression with a defines number of variables to be implemented.

A programmable array is essentially a grid of conductors forming rows and columns with a fusiblelink at each cross point. Each fused cross point of a row and column is called a cell and is the

programmable element of a PAL. Each row is connected to the input of an AND gate & is eachcolumn is connected to an input variable or its complement. By using the presence or absence of

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fused connections created by programming, any combination of input variables or complementscan be applied to an AND gate to form any desired product term.

Fig 5.1 Fig 5.2 [7]

HISTORY

Before PALs wereintroduced, designers of

digital logic circuits woulduse small-scale integration(SSI) components, such asthose in the 7400 seriesTTL (transistor-transistor logic) family; the 7400family included a variety of

logic building blocks, suchas gates (NOT, NAND,

NOR, AND, OR),multiplexers (MUXes) anddemultiplexers(DEMUXes), flip flops(D-type, JK, etc.) andothers. One PAL devicewould typically replacedozens of such "discrete"logic packages, so the SSI

business went into declineas the PAL business took off. PALs were usedadvantageously in many

products, such asminicomputers.

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PALs were not the firstcommercial programmablelogic devices; Signetics had

been selling its field programmable logic array(FPLA) since 1975. Thesedevices were completelyunfamiliar to most circuitdesigners and were

perceived to be too difficultto use. The FPLA had arelatively slow maximumoperating speed (due tohaving both programmable-

AND and programmable-OR arrays), was expensive,and had a poor reputationfor testability. Another factor limiting theacceptance of the FPLAwas the large package, a600-mil (0.6", or 15.24mm) wide 28-pin dual in-line package (DIP).

A circuit diagram to show the PALis shown below:

Fig5.3 [6]

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5. REFERENCES

WEBSITES

1. http://en.wikipedia.org/wiki/Programmable_logic_device

2. http://en.wikipedia.org/wiki/Programmable_ Logic _Array

3. http://en.wikipedia.org/wiki/Programmable_Array_Logic

4. http://cset.sp.utoledo.edu/eet3350/lesson1.html

5. http://www.absoluteastronomy.com/topics/Programmable_Arr ay_Logic

6. http://www.fys.uio.no/studier/kurs/fys4260/fig2-14.jpg

7. http://nomadicresearchlabs. com/store/images/components/PAL20L8.jpg

BOOKS

a. Floyd L; Jain R. P. , DigitalFundamentals, Pearson Education,Ed 8, 2008, Page-502 to 510

b. Bains G.S.;Walia M.S.,Digital Circuits and Logic Design,

PBS publication, Ed 2,2010, Page-269 to 272

http://en.wikipedia.org/wiki/Programmable_Array_Logichttp://en.wikipedia.org/wiki/Programmable_Array_Logichttp://cset.sp.utoledo.edu/eet3350/lesson1.htmlhttp://cset.sp.utoledo.edu/eet3350/lesson1.htmlhttp://www.absoluteastronomy.com/topics/Programmable_Array_Logichttp://www.absoluteastronomy.com/topics/Programmable_Array_Logichttp://www.absoluteastronomy.com/topics/Programmable_Array_Logichttp://www.fys.uio.no/studier/kurs/fys4260/fig2-14.jpghttp://www.fys.uio.no/studier/kurs/fys4260/fig2-14.jpghttp://nomadicresearchlabs.com/store/images/components/PAL20L8.jpghttp://nomadicresearchlabs.com/store/images/components/PAL20L8.jpghttp://nomadicresearchlabs.com/store/images/components/PAL20L8.jpghttp://nomadicresearchlabs.com/store/images/components/PAL20L8.jpghttp://en.wikipedia.org/wiki/Programmable_Array_Logichttp://en.wikipedia.org/wiki/Programmable_Array_Logichttp://cset.sp.utoledo.edu/eet3350/lesson1.htmlhttp://cset.sp.utoledo.edu/eet3350/lesson1.htmlhttp://www.absoluteastronomy.com/topics/Programmable_Array_Logichttp://www.absoluteastronomy.com/topics/Programmable_Array_Logichttp://www.absoluteastronomy.com/topics/Programmable_Array_Logichttp://www.fys.uio.no/studier/kurs/fys4260/fig2-14.jpghttp://www.fys.uio.no/studier/kurs/fys4260/fig2-14.jpghttp://nomadicresearchlabs.com/store/images/components/PAL20L8.jpghttp://nomadicresearchlabs.com/store/images/components/PAL20L8.jpghttp://nomadicresearchlabs.com/store/images/components/PAL20L8.jpg