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NODE IMPLEMENTATION

Submitted by

K. Raja Sekhar

1580910050

M.Vinod Kumar

1580910083

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Interconnect IPs can be classified

into several ways

Functionality

Number of links

Protocol options

Interconnect IPs

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An-IP Based On_chip

Packet_Switched Network

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Structure of FIFOs

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function

Size of buffer is defined by FIFO width and

length

Buffers are constructed from two sub blocks ,control logic and register bank

Register bank is the storage structure

Control updates

read and write pointers

When write request signal is asserted

incoming data isstored

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Contd

Output and input FIFOS are also accessedthrough a control port used to deliver resend

and delete commands

If the response is late , the output FIFO

receives a re-send command from the

interface block

Data cannot be deleted from the input FIFO The packets arriving to the input FIFO are

never re-sent

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LINK DEMULTIPLIXER

Receives packet through the input link

It detects the destination ID or the upper

address fields of the packet Comparing with its own IDs

If the test is positive the packet is written into

the inputFIFO

and later forwarded to theinterface block and host

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Link Multiplexer

The link multiplexer is used to transmit

packets from the FIFOs to the output link.

Link Multiplexer has a predefined priority thatis used to determine how packets are routed

from the FIFOs to the output link.

The priority is fixed when the network is

synthesized.

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Role of Design Parameters

Each node implementation is based on generic

parameters which define to the physical

structure of the network.

The parameters in below table are fixed at

compile time.

Route limits define the routing table in each

node: each output link has an associated

address range.

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Design Parameters

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Contd

The default priority favours the bypass FIFO

over the output FIFO.

This is used to prevent the generation of newtraffic until the old traffic is processed.

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Synthesis of Basic Node

There exist two implementation of interface IPs

because the VCI interface defines different properties

for the initiator and target of point-to-point

communication.

The following table presents gate-level area costs of

the initiator and target node, respectively. The cost

estimates are generated using synthesis and 0.18

micrometre silicon process.

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Implementation costs of basic proteo nodes in millimetre square.

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Disadvantage with FIFO

FIFOs consume a very significant area.

Using memories it should be possible to

reduce the area of FIFOs significantlycompared to the current situation.

But memory based FIFOs are yet to be

realized.

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THANKYOU

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