7/25/2019 Altera Time
1/20
BR 1/99 1
Logic
Elementarray
PIN
Altera IO Element
7/25/2019 Altera Time
2/20
BR 1/99 2
PIN
Tincomb
Tiod Tiocomb Tod1
Altera IOE Timing model
7/25/2019 Altera Time
3/20
BR 1/99 3
IOE Delay
! In"#t "at$% Tincomb & in"#t "ad and b#''er to 'attrac( interconnect
delay
! O#t"#t "at$ )combinatorial "at$ *it$ 'at o#t"#t
le*+
% Tiod & data delay
% Tiocomb & combinatorial delay
% Tod1 & lo* rate , o''- .ccio , .ccint ).cc o' IO "ad iame a internal .cc+
7/25/2019 Altera Time
4/20
BR 1/99 0
Aide $y "rogrammable O#t"#t le*
! 4le* rate i t$e mea#re o' $o* 'at an o#t"#t canc$ange 5al#e )mea#red in .olt/4ec+
! 6ot 7P8A 5endor o''er t$e ca"ability o'
"rogramming t$e o#t"#t to be eit$er 'at le* or
lo* le* &&&&& :
% 7at 4le* rate ca#e more noie "roblem 5ia gro#nd
bo#nce- e"ecially *$en m#lti"le o#t"#t are *itc$ing
%I' yo# $a5e room in yo#r timing "ec- $o#ld #e lo*le* rate i' "oible
7/25/2019 Altera Time
5/20
BR 1/99 ;
8ND Bo#nce
7/25/2019 Altera Time
6/20
BR 1/99 C
Altera Logic Element
7/25/2019 Altera Time
7/20
BR 1/99
Tl#t Tcomb
Altera Logic Element
7/25/2019 Altera Time
8/20
BR 1/99
6inim#m Pin To Pin Delay
[Input Pin delay] + [Logic Element Delay] + [Output Delay]
[Tincomb] + [Tlut + Tcomb] + [Tiod + Tiocomb + Tod1]
$at abo#t Ro#ting Delay Table 2? $a ro#ting delay
Tdin2data & delay 'rom dedicated in"#t or cloc( to LE data
Tamecol#mn & delay 'rom LE o#t"#t to IOE in ame col#mn
Tamero* & delay 'rom LE o#t"#t IOE in ame ro*
7/25/2019 Altera Time
9/20
BR 1/99 9
6inim#m Pin To Pin Delay
[Input Pin delay] + [Routing] + [Logic Element Delay] + [Routing] +[Output Delay
[Tincomb] + [Tdin2data] + [Tlut + Tcomb] +
[Minimum (ame col!"o#$] + [Tiod + Tiocomb + Tod1]
[ 2%& ] + ['%] + [1%' + )%*] + min(1%'!%$ + [ 1% +)%) + 2%,]
- 1'% n
i' ignore ro#ting- t$en C n )t$i i *$at mar(eting *illF#ote+
Note t$at ame col#mn ro#ting m#c$ 'ater t$an ro* ro#ting
)$ence dedicated carry c$ain r#n in col#mn ro#ting+
7/25/2019 Altera Time
10/20
BR 1/99 1?
6inim#m Regiter to Regiter
[Input Pin delay] + [Routing] + [Logic element cloc./to/0] + [Routing] +
[Logic Element Delay] + [Routing] + [Logic Element etup Time]
Dedicated
7/25/2019 Altera Time
11/20
BR 1/99 11
6inim#m Regiter to Regiter
[Input Pin delay] + [Routing] + [Logic element cloc./to/0] + [Routing] +
[Logic Element etup Time]
Dedicated
7/25/2019 Altera Time
12/20
BR 1/99 12
Dedicated In"#t/
7/25/2019 Altera Time
13/20
BR 1/99 13
4et#" Time 'or Logic Element
D77
GDLHTT# orT# Tl#t
Ty"ically- t$e et#" time "eci'ication 'or an e>ternal
data in"#t already acco#nt 'or t$e LHT delay ince t$e
data in"#t $a to "a t$ro#g$ t$e LHT on it *ay to
t$e D in"#t
T$e altera "ec i a bit con'#ing & my bet g#e i t$at
T# incl#de t$e LHT delay T$ere i no do#bt t$at t$e
Kilin> .irte> T# "ec incl#de t$e LHT delay
7/25/2019 Altera Time
14/20
BR 1/99 10
7/25/2019 Altera Time
15/20
BR 1/99 1;
7/25/2019 Altera Time
16/20
BR 1/99 1C
Latc$ing in IOE or LE
! T$e D77 in t$e IOE can be con'ig#red to eit$erlatc$ incoming data or o#tgoing data
%
7/25/2019 Altera Time
17/20
BR 1/99 1
6inim#m E>ternal 4et#" Time
Data latc$ed in LE
Ro#tingt , 31 n 10n
13n & ? , ; n
In"#t
T#e>tD
7/25/2019 Altera Time
18/20
BR 1/99 1
6inim#m E>ternal 4et#" Time
Data latc$ed in IOE
Ro#tingt , C? n 2 & ? , n
D
Latc$ing in IOE lo*er t$an in
Logic Element T$ee are all *ore
cae n#mber in t$e data$eet *$ic$co#ld acco#nt 'or t$iM alo mentioned
on "age 2 t$at latc$ing in LE
element *ill ometime gi5e better
et#" time t$an an IOE 7or ot$er
7P8A 'amilie t$i i ##ally not t$e
cae
7/25/2019 Altera Time
19/20
BR 1/99 19
t+ *ill be
contraint on $o* 'at data
i e>c$anged bet*een c$i"
7/25/2019 Altera Time
20/20
BR 1/99 2?
PLL e''ect
PLL/DLL *ill ync$roniJe internal cloc( to e>ternal
cloc( Aim i to $a5e Jero delay bet*een cloc( edge at
Logic element and e>ternal cloc( edge
Ro#ting
GLHT
Dedicated