CNR-IFSI 1
PACS IIDR 01/02 Mar 2001
DPU Subsystem Presentation
Renato Orfei
CNR-IFSI
CNR-IFSI 2
PACS IIDR 01/02 Mar 2001
General Block Diagram
DPU-OM SPU-NOM
S/C
MEC 2MECH-CONTRO 2LWL DETECTOR
CONTROL
PACS S/S
SWL DET.
GRATING ASS.
CHOPPERASS.
FLIP MIRRORASS.
LWL DET.
MEC 1MECH-CONTROL1SWL DETECTOR
CONTROL
DPU-RED SPU-RED
CNR-IFSI 3
PACS IIDR 01/02 Mar 2001
FPGAState
Machine
ONE Serial I/FTo/From
DEC/MEC
512 Kw2 MB
262 Kw1 MB
5.4 Kw32 KB
512 Kw3 MB
Dat
a ar
ea32
bit
wor
dsPr
ogra
m a
rea
48 b
it w
ords
ICUTSC 21020
DSP
DataRAM
EEPROMInst. Program
Program RAMInstr. Program
From EEPROMS/C
TWO Serial I/FTo/From
SPU
PROMKernel Telemetry
upload SW
DPU General Block Diagram
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PACS IIDR 01/02 Mar 2001
DPU High level block diagramLVDS
PL I/FPL I/FPL I/F
CPUCPUCPU PL I/FPL I/FPL I/F
CPUCPUCPU
MAIN
REDUNDANT
Parallel busParallel bus
S/C 1553 BUS
S/CS/Cppoowweerr
bbuuss
Parallel busParallel bus
13551355
POWER SUPPLY
POWER SUPPLY
13551355
1553 I/F
1553 I/F
1355 I/F
1355 I/F
DC/DC CONV.MAIN
DC/DC CONV.REDUNDANT
LVDS
PDUPDU
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PACS IIDR 01/02 Mar 2001
20 M HzCLOC K
DATA M EMORY
T SC 21 020
JTAGC ONN ECTOR
SYST
EM
CO
NNE
CT
OR
1
SYST
EM
CO
NNE
CT
OR
2
INTER RU PTMANAG ER
WA TC HD OG
16-BIT BU SINTER FAC E
NO T US ED
CONTROLLOGIC
C ONTR OL FPGA
BO OTLOG IC
M EZZANIN EINTER FAC E
SM CS(TEM IC TSS 90 1)
DU ALPORTRAMIE EE 1 355
INTER FAC E
1355 LIN K 1
1355 LIN K 2
1355 LIN K 3
LATCH
LATC H
LATC H
BOOT LOGIC(INSID E
C ONTR OLF PGA )
BO OT MA NA GER
512Kx48SRA M
Expan ded
P ROGR A M M EMO RY
5 12 K BE EPR OM
MEZZ A NIN E
MEZ
ZAN
I NE
CONN
ECT
OR
A
MEZ
ZAN
I NE
CONN
ECT
OR
B
P R O M 32 K B
5 12 K BE EPR O M
INTER VA LTIME R
512Kx32SRA M
Expan ded CPU Block Diagram
CNR-IFSI 6
PACS IIDR 01/02 Mar 2001
TRc
TRd
TRe
TRa
Lb
Lc
Ld
5V
15 V
-15 V
28 V
EMC FILTER
OvercurrentProtection
Start upCircuit
Driver
Rectification andsecondary filters
DC/DC Converter Block Diagram
CNR-IFSI 7
PACS IIDR 01/02 Mar 2001
28VRET
FILTER
RET
DC/DC
Sync
BondStub
.
Nom
Red
S/CTM/TC
SPULWL
SPUSWL
DEC/MEC
PRIMARY
DC/DC CONVTransf.
DPU GROUNDING SCHEME
BALANCEDDRIVERS
BALANCEDRECEIVERS
Common Mode Transf.
jumper jumper
jumper
OR
Prime
Red.
Synch.
LVDS
CNR-IFSI 8
PACS IIDR 01/02 Mar 2001
CNR-IFSI 9
PACS IIDR 01/02 Mar 2001
DPU Mass breakdown
• Components of the mass breakdown:BOX (240x258x194 mm^3, thickness 3 mm, 2.7 g/cm^3):
Baseplate 240x258x3= > 501.5 g Front wall: 240x194x3=> 377.1 gFront wall connectors (delta:E)=> 150 gBak wall: 240x194x3=> 377.1 gLateral walls: 258x194x3x2=> 754.3 g Cover: 240x258x3=> 501.5 g Total Box weight: 2661.5 g
• CPU boards: 2x 600 g => 1200 g• P/L I/F Boards: 2x 480 g => 960 g• DC/DC boards: 1000 g => 1000 g• Motherboard: 400 g => 400 g• Screws etc.: 100 g => 100 g• Cabling: 300 g => 300 g
Total estimated weight: 6621.5 g (+ - 10 %)
CNR-IFSI 10
PACS IIDR 01/02 Mar 2001
CDMS COMMUNICATION I/F
CNR-IFSI 11
PACS IIDR 01/02 Mar 2001
28 V lines S/C operated plus synchronization from S/C to PACS:
POWER SUPPLY I/F
• One I/F for DPU DC/DC converter • Other I/Fs for SPU and DEC/MEC controlled by DPU via “Event Pkt”
CPU
CDMS Event Pkt
S/C DPU
28Vswitches
DC/DC DC/DC
SPU & DEC/MEC
CNR-IFSI 12
PACS IIDR 01/02 Mar 2001
Subsystems InterfacesAll HW interfaces implemented with balanced drivers and receivers (LVDS)
• 3 high speed serial bi-directional links for science data and HK collection: - 2 links to/from SPU-1 link to/from DEC/MEC
• The links will be used for subsystems commanding and reception of science and HK data
CNR-IFSI 13
PACS IIDR 01/02 Mar 2001
decoder (in FPGA)decoder (in FPGA)decoder (in FPGA)
BU61582 (BU61580 for EM and EQM)BU61582 (BU61580 for EM and EQM)
16_BIT16_BITADDRADDR __ LATLAT
A0-A13A0-A13D0-D15D0-D15
\\ INTINT
\\READYDREADYD
RD\RD\ WRWR\\STRBDSTRBD
\SELECT\SELECTMEMMEM \\REGREG
POLARITY_POLARITY_ SELSEL
RTAD0-4RTAD0-4
D15-D0 D15-D0
A13-A0A13-A0
\BUFFERED\BUFFERED
+5V+5V
+5V+5V
+5V+5V\ZERO_ WAIT\ZERO_ WAIT
+5V+5V
GNDGND
JUMPERJUMPER
SysemBus
SysemBus
16MHz clockOscillator
16MHz clockOscillator
CLKCLK ININ
IRQM7IRQM7
JUMPERJUMPERSACKSACK
FLAG1FLAG1
ACKManager(in FPGA)
ACKACKManagerManager(in FPGA)(in FPGA)
ACK lines comingACK lines comingfrom other peripheralsfrom other peripherals
Long Stub Configuration
CH. A
CH. B
TX/TX/ RXARXA
\TX/\TX/ RXARXA
TX/TX/ RXBRXB
\TX/\TX/ RXBRXB
RTADPRTADP
+5V+5V
pull-up
+5V+5V
pull-uppull-up
\\ INCMDINCMDSTATUSSTATUS REGREG ..TAG_TAG_ CLKCLK +5V (TBC)
S/C Interface Block diagram
CNR-IFSI 14
PACS IIDR 01/02 Mar 2001
ID Task Name Duration Start0 PACS_WP 1458 days Wed 01/07/98
1 DPU design 87 wks Wed 01/07/98
2 Computer architecture 76 wks Mon 20/07/98
3 S/C I/F design 87 wks Wed 01/07/98
4 Subsystems I/F design 82.4 wks Mon 03/08/98
5 DPU ITT 40 wks Mon 11/10/99
6 DPU requirements 12 wks Mon 11/10/99
7 ITT 16 wks Mon 29/11/99
8 Industry selection 1 wk Mon 20/03/00
9 Sign of contract 16 wks Mon 27/03/00
10 Simulators 0.2 wks Tue 15/05/01
11 SPU Simulator at IFSI 0.2 wks Tue 15/05/01
12 DEC/MEC Simulator at IFSI 0.2 wks Tue 15/05/01
13 EGSE at IFSI 0.2 wks Tue 15/05/01
14 AVM 73.8 wks Tue 01/08/00
15 PDR 0.2 wks Thu 01/03/01
16 Electrical mfg 48 wks Tue 01/08/00
17 Mechanical mfg 14 wks Tue 27/03/01
18 Electr. Boards to IFSI 1 wk Mon 02/07/01
19 Assembly 5 wks Mon 09/07/01
20 In house tests 20 wks Mon 06/08/01
21 Delivery to MPE 1 wk Mon 24/12/01
22 QM 37.2 wks Mon 15/10/01
23 Author. To Proceed 0.2 wks Mon 15/10/01
24 Electrical mfg 15 wks Tue 16/10/01
20/03
15/05
15/05
15/05
01/03
02/07
24/12
15/10
Qtr 4 Qtr 1 Qtr 2 Qtr 3 Qtr 4 Qtr 1 Qtr 2 Qtr 3 Qtr 4 Qtr 12000 2001 2002
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PACS IIDR 01/02 Mar 2001
ID Task Name Duration Start25 Mechanical mfg 10 wks Tue 20/11/01
26 Electr. Boards to IFSI 1 wk Tue 29/01/02
27 Assembly 7 wks Tue 05/02/02
28 In house tests 9 wks Tue 19/03/02
29 Envir. Tests 5 wks Tue 21/05/02
30 Delivery to MPE 1 wk Tue 25/06/02
31 PFM 54.6 wks Thu 12/09/02
32 CDR 0.2 wks Thu 12/09/02
33 Author. To Proceed 0.2 wks Fri 20/09/02
34 Electrical mfg 22 wks Tue 01/10/02
35 Burn of flight PROMs 2 wks Tue 18/02/03
36 Mechanical mfg 12 wks Tue 10/12/02
37 Electr. Boards to IFSI 1 wk Tue 04/03/03
38 Assembly 10 wks Tue 11/03/03
39 In house tests 14 wks Tue 13/05/03
40 Envir. Tests 5 wks Tue 19/08/03
41 Delivery to MPE 1 wk Tue 23/09/03
42 FS 59.6 wks Thu 21/11/02
43 Electrical mfg 22 wks Thu 21/11/02
44 Electr. Boards to IFSI 0.2 wks Thu 22/05/03
45 In house tests 15 wks Tue 19/08/03
46 Envir. Tests 5 wks Tue 02/12/03
47 Delivery 1 wk Tue 06/01/04
29/01
25/06
12/09
20/09
04/03
23/09
22/05
06/01
Qtr 4 Qtr 1 Qtr 2 Qtr 3 Qtr 4 Qtr 1 Qtr 2 Qtr 3 Qtr 4 Qtr 12002 2003 2004
CNR-IFSI 16
PACS IIDR 01/02 Mar 2001ID Task Name48 OBS
49 Reviews
50 Req/Arch design
51 AVM TRR
52 AVM Delivery
53 PFM TRR
54 PFM delivery
55 Development
56 S/C I/F module
57 Subsys. I/F mod.
58 OBS Controller
59 Data packetiser
60 OBS intermediate review
61 Health autonomy mod
62 AVM issue
63 OBS 2nd review
64 PFM issue
65 Documentation
66 URD - User Requirement Doc
67 SSD - SW specification Doc
68 DDD - Detail design doc
69 SVVP - SW validation and verification plan
70 OBS User Manual
71 Support activities
72 Virtuoso OS
73 Decision on OS use
74 Test mod.
02/04
17/12
24/12
16/09
23/09
02/04
08/01
Qtr 1 Qtr 2 Qtr 3 Qtr 4 Qtr 1 Qtr 2 Qtr 3 Qtr 4 Qtr 1 Qtr 2 Qtr 3 Qtr 4 Qtr 1 Qtr 22001 2002 2003 2004
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